Accurate high-speed clock signals are often used for transmitting and receiving data in high-speed circuits, such as high-speed memory devices or high speed bus channels. However, high speed clock signals often become distorted during transmission and reception. Consequently, high speed circuits, such as dynamic random access memory (DRAM) devices, often recover an externally provided high-speed clock signal by locking an accurate internally generated clock signal to the distorted externally provided clock signal.
A delayed locked loop (DLL) is typically used to delay the internally generated clock signal in order to match the phase of the internally generated clock signal to the phase of some reference clock signal. Typically, a phase-detection circuit in the DLL compares the phase of the internal clock signal to the reference signal and a control-logic block that is coupled to the output of the phase-detection circuit is used to increase or decrease a delay produced by a chain of delay elements used to delay the internal clock signal. U.S. Pat. Nos. 5,945,862 and 6,125,157 to Donnelly et al. represent two approaches to locking an internal clock signal to an external clock signal using delay elements.
It is desirable to provide for a fully digital DLL circuit that can be fabricated using standard digital design techniques.